A time-interleaved (TI) analog-to-digital converter (ADC) architecture increases the effective conversion rate of an ADC by multiplexing several ADC “channels” in parallel. In a time-interleaved structure, the effective sampling rate can be increased by n times, by having n time-interleaved channels.
FIG. 1 shows a block diagram of a conventional TI ADC architecture including multiple TI ADCs 120a-n. The respective TI ADCs sample an input signal 102 at interleaved timing based on a plurality of clock signals 1031-n (also shown in FIG. 1 with labels T1-TN) applied to sample/hold (S/H) circuits 1051-n. The combination of one TI ADC and its corresponding S/H circuit is sometimes referred to as a TI ADC “channel.” When the digital outputs 1221-n of the respective TI ADCs (or TI ADC channels) are combined and placed in an interleaved sequence by a multiplexer 150, the collection of TI ADC channels functions effectively as a single converter operating at a higher conversion rate (the effective conversion rate (fs) of a TI ADC architecture can be expressed as fs=fc·n, where fc is the conversion rate of each channel and n is number of the interleaved channels; thus, the effective conversion rate can be increased linearly by interleaving more channels). The TI ADC architecture can be applied to most ADC architectures, some examples of which include flash, folding, pipelined, successive approximation (SAR), single slope, and sigma-delta architectures.
Conventional TI ADC architectures generally provide for increased power efficiency. In non-time-interleaved conventional ADCs, the power consumption of an ADC generally grows much faster than proportional to the conversion rate of the ADC. However, in the time-interleaved architecture shown in FIG. 1, the effective conversion rate can be increased by n times at the cost of only n times power consumption. Although there is some additional power overhead due to components that facilitate the TI ADC architecture (e.g., an interleaved clock generator and a digital output combiner), this additional power overhead is typically an insignificant portion of the overall power consumption.
The resolution of a TI ADC architecture overall is the same as the resolution of the ADC in each channel. However, in some implementations, mismatches between the channels introduce additional error sources that limit the accuracy of the analog to digital conversion. Because most errors from conventional TI ADC architectures appear as harmonics and spurs in the output spectrum, these types of errors are especially detrimental to applications which require high Spurious-Free Dynamic Range (SFDR).
The effective sampling rate of the TI ADC architecture may not be increased arbitrarily high due to some practical limitations. The sample and hold (S/H) circuits 1051-n shown in FIG. 1 present one such limitation; namely, the S/H circuits 1051-n should be fast enough to track the input signal accurately up to the speed and resolution of the corresponding TI ADC in the channel. Thus, the ultimate effective sampling rate is limited by the bandwidth of the S/H circuit. Furthermore, the area and on-chip wiring of a TI ADC architecture sets a practical limitation on the number of channels. Because of the parallel structure, the area and cost of TI ADCs 120a-n increase linearly with the number of channels. Also, it is difficult to connect sensitive signals, such as the input analog signal and the clock signals, over a wide area without introducing some degree of mismatch and noise. Thus, increasing the number of interleaved channels can in some respects degrade overall performance of the TI ADC architecture.
Another issue with the conventional TI ADC architecture shown in FIG. 1 relates to offset and mismatch. The offset of an ADC manifests itself as a static value added at the input regardless of the input signal. A fixed amount of error caused by random variation, such as charge injection from the sampling switches and the offsets of comparators and amplifiers, can cause ADC offsets. The offset of a single channel ADC appears as a DC signal in the frequency domain and does not degrade the dynamic performance of the ADC.
In TI ADCs 1201-n, however, the offset mismatches between channels generates tones at the frequencies that are multiples of
      fs    n    .FIG. 2 snows an example of me offset errors (301) in a 4-channel TI ADC. In the time domain, the error from the offset mismatches 301 is periodic with a frequency of
      fs    4    .Thus, this error appears as multiple tones at the frequencies of
  0  ,      fs    4    ,            2      ⁢      fs        4    ,            3      ⁢      fs        4  in the frequency domain 300. Because the offset error does not vary with the input signal 102, the amplitude and frequency of the error tones are independent of the input signal 102. Another way of analyzing TI ADC offset error is that the mean of the offsets of the interleaved channels (e.g., see graph 302) is the offset of the TI ADC and the deviation of the offsets from the interleaved channels (e.g., see graph 303) causes spurs at frequencies of
      fs    4    ,            2      ⁢      fs        4    ,                    3        ⁢        fs            4        .  
The offset of each ADC channel can be defined as the y intercept of the best fit line of each ADC transfer function. The calibration of offset mismatches can be done in either the analog domain or the digital domain. Digital offset calibration means an addition or subtraction of an offset value at the digital output. This can be done easily with low power consumption, but, due to the quantization level, the remaining error can be as large as ½ Least Significant Bits (LSBs) of the ADC. On the other hand, the offset calibration in the analog domain can have better accuracy at the cost of additional power and increased circuit complexity.
The gain of an ADC is the slope of the best fit line of the ADC transfer function. Ideally, the gain is equal to 1, but several error sources, such as capacitor mismatches and variations in the reference voltage, cause gain error. In a single channel ADC, gain error changes the amplitude of the output signal, but does not degrade the dynamic performance of the ADC.
The effect of gain mismatches in a four channel TI ADC is described in FIG. 3 (e.g., see graph 401). Errors from gain mismatches are Δgi·vin, where Δgi is the gain error of the ith channel and vin is the input signal (102 in FIG. 1). In the time domain, this error can be analyzed as a product of the periodic sequence of Δg1, Δg2, Δg3, Δg4 (e.g., see graph 403) and the input signal vin, which can be time-variant (e.g., see graph 402).
Thus, the result in the frequency domain 300 can be calculated by the convolution of the two spectra. Because the periodic sequence of Δg1, Δg2, Δg3, Δg4 have four tones at frequencies of
  0  ,      fs    4    ,            2      ⁢      fs        4    ,            3      ⁢      fs        4    ,the spurs appear at
      0    ±          f      in        ,      fs    4    ,      ±          f      in        ,            2      ⁢      fs        4    ,      ±          f      in        ,                    3        ⁢        fs            4        ±          f      in      in the frequency domain 300. This is different from the offset errors in that the frequencies of the error tones depend on the input frequency, and the amplitude of the error tones increases linearly with the amplitude of the input signal 102. Multiplications at the digital output can be used for gain-error correction. The digital multiplication increases hardware and power consumption compared to the addition needed for offset calibration.
Another issue with the TI ADC architecture shown in FIG. 1 is referred to as time-skew error. The clock signals 1031-n shown in FIG. 1 (or φ1, . . . φ4 as shown in the data plot in FIG. 5) are usually generated on-chip by dividing a high frequency clock. Ideally, the clocks should be uniformly spaced in time. However, due to unavoidable mismatches in layout, random mismatches in clock generator circuits, and random variations of the threshold voltage in the sampling switches, the clock edges often deviate from the ideal case and are spaced non-uniformly, as shown in FIG. 4 by Δt1, Δt2, Δt3, and Δt4. This error of the clock edges in time is called “timing-skew” (and is generally denoted in FIG. 4 with the reference numeral 502). Timing-skew is a unique and additional error source of the TI ADC architecture which does not happen in a single channel ADC.
When a pure single tone signal is applied to the input, the errors from the timing-skew can be expressed as
                                          v            IN                    ⁡                      (            t            )                          =                  A          ⁢                                          ⁢                      ⅇ                          j              ⁢                                                          ⁢                              w                in                            ⁢              t                                                          (        1        )                                                                                    e                                  skew                  ,                  i                                            =                            ⁢                                                                                          ⅆ                                                                        v                          in                                                ⁡                                                  (                          t                          )                                                                                                            ⅆ                      t                                                        ·                  Δ                                ⁢                                                                  ⁢                                  t                  i                                                                                                        =                            ⁢                              j                ⁢                                                                  ⁢                                  w                  in                                ⁢                A                ⁢                                                                  ⁢                                                      ⅇ                                          j                      ⁢                                                                                          ⁢                                              w                        in                                            ⁢                      t                                                        ·                  Δ                                ⁢                                                                  ⁢                                                      t                    i                                    (                  3                  )                                                                                                        =                            ⁢                              j                ⁢                                                                  ⁢                                  w                  in                                ⁢                Δ                ⁢                                                                  ⁢                                                      t                    i                                    ·                                                            v                      IN                                        ⁡                                          (                      t                      )                                                                      ⁢                                  (                  4                  )                                                                                        (        2        )            where Δti is the timing-skew 502 of the ith channel. Similar to the gain error case shown in FIG. 4, the error from timing skew can be analyzed as a product of the periodic sequence of jwΔt1, jwΔt2, . . . , jwΔtN and the input signal VIN (102).
FIG. 5 shows an example of the timing-skew error (e.g., see graph 601) in a four channel interleaved ADC. Note that the frequencies of the error tones are the same as the frequency of the tones generated by gain mismatches in the frequency domain 300. This shows that timing-skew and gain errors may not be distinguished from the frequency of the error tones. However, there is an important difference between the gain errors (shown in graph 501) and timing-skew errors (shown in graph 601) that allows the two error sources to be separated. As derived in Equation (4), the timing-skew errors are proportional to the input frequency (e.g., see graph 603), while the errors from gain mismatches are independent of the input frequency. Thus, the gain error can be measured and calibrated from a low frequency input test and the timing-skew errors can be processed later with a high frequency input test.
Considering that the conventional TI ADC architecture shown in FIG. 1 typically is employed to expand the bandwidth of input analog signals for conversion to digital outputs, in practical applications the input analog signals of interest tend to have relatively high frequency components. Unfortunately, given the above-noted relation between the timing-skew error and input frequency, timing-skew errors can thus constitute a dominant source of conversion error in the TI ADC architecture. For example, the timing-skew requirement for a 10 bit 1 GS/s TI ADC can be roughly calculated as follows:
                                          e                          skew              ,              i                                            v            in                          <                  1                      2            N                                              (        5        )                                                      Δ            ⁢                                                  ⁢                          t              i                                <                      1                                          w                max                            ·                              2                N                                                    =                              1                          2              ⁢              π              ⁢                                                          ⁢              0.5              ⁢                                                e                  9                                ·                                  2                  10                                                              ≈                      300            ⁢                                                  ⁢            fs                                              (        6        )            
Generally, conventional timing-skew calibrations are processed in two steps: timing-skew measurement (or estimation) and error correction. Timing skew can be measured with a predetermined input signal such as a linear ramp or a sine wave with known frequency and amplitude. This makes the measurement relatively easy and accurate. However, to apply such a specific input signal, the normal ADC operation is interrupted to allow for the calibration. Timing-skew is sensitive to temperature and supply voltage changes. Temperature and supply voltage change the sharpness of clock transition edges, which in turn affect the timing-skew caused by random variation of the threshold voltage in the clock generators. The ability to track variations in the timing-skew is an important aspect of the calibration. Thus, these calibrations are limited to applications where ADCs are allowed to a have an off-phase for a foreground calibration (i.e., an interruption to the normal operation of the ADC to sample an input analog signal and provide a corresponding digital output).
Timing-skew can also be measured with arbitrary inputs, which allows for some types of background calibration. In one conventional example, a correlation-based algorithm can be used to measure the timing-skew. A dedicated timing reference TI ADC channel which does not suffer from timing-skew can be used as a reference for the TI ADC channels that are actively sampling and converting an input analog signal. For example, two additional TI ADC channels dedicated to a direct measurement of the timing-skew error can be used. One such TI ADC channel dedicated to calibration serves as a reference for the other “active” TI ADC channels that are sampling and converting the input analog signal, and the other TI ADC channel dedicated to calibration is used to measure the derivative of the input signal. In this example, the additional dedicated TI ADC channels required for the calibration are an expensive overhead.
The correction of timing-skew error can be done in either the digital domain or the analog domain. Digital interpolation filters, fractional delay filters, and Taylor series approximations are examples of digital filters for timing-skew calibration. Although these techniques can be demonstrated in simulation, only a few implementations of these techniques (e.g., in actual silicon chips) have been reported to date in the literature. This is not surprising, as the cost in power consumption and area of the digital calibration block is significant, even in modern CMOS technology.
In another example, programmable-delay blocks are placed at the sampling clock to compensate the timing-skew. This is the most practical and frequently used conventional solution. However, this technique also suffers from some drawbacks in that it tends to increase the noise and jitter of the clock signals used for sampling in the TI ADC channels. The impact of clock jitter is usually negligible for low-performance ADCs, but it becomes more notable for high-speed and high-resolution ADCs. Thus, when sampling speed is improved with TI ADC architecture, clock jitter can limit the accuracy of digital output. Unlike timing-skew, due to its random characteristics, clock jitter increases the noise floor of the output spectrum, but does not cause spurs. The requirement of the clock jitter can be calculated similarly to Equation (6) above.